1. Field of the Invention
The present invention relates to a BiCMOS semiconductor device and a production method thereof.
2. Description of Related Art
In recent years, a semiconductor device wherein a bipolar transistor, for example, is formed simultaneously on a system LSI including a CMOS comprising a MOSFET (metal oxide semiconductor field-effect transistor) has been developed.
In Japanese Unexamined Patent Publication No. 2008-021671, a blocking layer for blocking the formation of a strain-imparting semiconductor region in a strained channel MOSFET is formed around a base region separated by an element separation layer, with the same process as that for forming the gate electrode section of a CMOS, thus allowing an emitter region formed simultaneously with the epitaxial growth of the strain-imparting semiconductor region to undergo epitaxial growth while being separated from the element separation layer. This document states that this technique avoids the occurrence of defects when the emitter region is formed in contact with the element separation layer, thus improving transistor characteristics without increasing the number of processes.
Meanwhile, in a MOSFET, a silicide layer is formed over the surface of a diffusion region constituting a source/drain region in order to decrease contact resistance with the source/drain region. In BiCMOS devices the bipolar transistor should be formed simultaneously in the CMOS forming process, to avoid additional processes. Thus, when a MOSFET and a bipolar transistor are formed simultaneously on a substrate, a silicide layer is also formed over the surface of a diffusion region constituting the bipolar transistor.
U.S. Pat. No. 6,352,887 describes a BiCMOS integrated circuit wherein a silicide layer is formed over the surface of a diffusion region. In particular, a photoresist is deposited at the end of an emitter region and over a field oxide region adjacent to the emitter region so as to cover a part of a laminated layer comprising a gate oxide layer and a silicide mask oxide; and an exposed gate oxide layer is removed. Thereafter, titanium is deposited to a thickness of about 30 nm, heat is applied at about 675° C. for about 30 minutes, and thus a silicide layer is formed at a site where the silicide mask oxide is not formed. This document states that, the absence of silicide at the periphery of the emitter reduces the chance of degraded gain (hfe) from recombination effects at the emitter edge that result from uneven silicide thickness or spiking at the bird's beak region.